1. Field of the Invention
The present invention relates to an input buffer circuit, and more particularly, to an input buffer circuit that improves a noise margin.
2. Background of the Related Art
As shown in FIG. 1, in a related art input buffer circuit there are serially connected a plurality of inverters 1, 2 between an input terminal IN and an output terminal OUT. The input buffer circuit compares a logic threshold voltage Vth and an input voltage and outputs the resultant value. That is, as shown in FIG. 2A, when the input voltage IN is lower than that of the logic threshold voltage Vth, the inverter 1 recognizes the input value as a low level and outputs a high level signal. Accordingly, the output signal OUT becomes low level because of the inverter 2 as shown in FIG. 2B.
To the contrary, as shown in FIG. 2A, when the input voltage IN is higher than that of the logic threshold voltage Vth, the inverter 1 recognizes the input value as a high level and outputs a low level signal. Accordingly, the output signal OUT becomes a high level because of the inverter 2 as shown in FIG. 2B.
However, in the related art input buffer circuit, when an input voltage is converted around a logic threshold voltage, the input circuit does not exactly recognize the input voltage as an appropriate high or low level. In this case, the operation of the input circuit becomes unstable and accordingly incurs noise.